The GC4016 quad receiver chip contain four identical down-conversion circuits. Each downconvert circuit accepts a real sample rate up to 100 MHz, down converts a selected carrier frequency to zero, decimates the signal rate by a programmable factor ranging from 32 to 16,384 and then resamples the channel to adjust the sample rate up or down by an arbitrary factor. In the real output mode the output sample rate is doubled and the signal is output as a real signal centered at F_out/4. The channels may be combined to produce wider band and/or oversampled outputs or to process complex input data. The chip outputs the down-converted signals in any one of several formats (microprocessor, four serial lines, one TDM serial line, nibble, LINK, or 24 bit parallel port.