This 9-bit, 4-port universal bus exchanger is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH16409 allows synchronous data exchange between four different buses. Data flow is controlled by the select (SEL0-SEL4) inputs. A data-flow state is stored on the rising edge of the clock (CLK) input if the select-enable (SELEN\) input is low. Once a data-flow state has been established, data is stored in the flip-flop on the rising edge of CLK if SELEN\ is high.

The data-flow control logic is designed to allow glitch-free data transmission.

When preset (PRE\) transitions high, the outputs are disabled immediately, without waiting for a clock pulse. To leave the high-impedance state, both PRE\ and SELEN\ must be low and a clock pulse must be applied.