本文提出一種基于多位MASH（Multi-stAge-noise-Shaping）結構Δ-Σ 調制器的新型DPWM（Digital-Pulse-Width-Modulator）方法，在詳細論述該DPWM 方法原理的基礎上，并以同步整流Buck變換電路為例，基于Virtex-Ⅱ FPGA 控制策略，實現了高達4MHz 的開關頻率和11 位的有效分辨率DPWM。仿真和實驗結果證明了該控制器的可行性和有效性。
Abstract: This paper proposed a novel multi-bit Delta-Sigma (Δ-Σ) concept of Multi-stAge-noise-SHaping (MASH) modulator. The principle of the DPWM was introduced in detail. The implementation techniques are experimentally verified using a Virtex-II FPGA and a discrete low-power synchronous buck converter. In these conditions the proposed controller can operate at programmable constant switching frequency up to 4MHz with 11-bit effective DPWM resolution
關鍵詞：數字控制，多位MASH 結構Δ-Σ DPWM，FPGA 實現
Keywords: Digital Control, multi-bit Delta-Sigma (Δ-Σ) MASH modulator, FPGA implementation