本文主要設計了基于相位控制技術的時鐘恢復系統的PLL 鎖相環路。分別對各單元
電路結構——鑒頻鑒相器、電荷泵、環路濾波器、壓控振蕩器、分頻器進行設計。采用2.5V，0.25μm First Silicon CMOS 工藝來實現，并在SPICE 平臺下進行仿真。仿真結果表明，該PLL 環路的鎖定時間僅為2.4us，并且輸出的頻譜呈現出較高的純度，具有高速、低噪聲的特點。
關鍵詞：鎖相環；電荷泵；噪聲

The Design of PLL Circuits Based on Clock Recovery System YIN Wei1,2，ZHANG Hong-nan1， HUANG Ya-you1，ZENG Yun1 (1. College of Physics and Microelectronics Science, Hunan Univ.,Changsha，Hunan 410082, China; 2. Electron engineering department, Hunan Yueyang professional technology college,Yueyang,Hunan 414000,China) Abstract: In this paper, a PLL circuits based on clock recovery system which based on phase controlled technology is studied. All units were designed by the following orders——PFD、charge
pump、LPF、VCO and frequency divider. All the design is fabricated in a 2.5V, 0.25μm first silicon CMOS process. The simulation results show that the acquisition time is only 2.4us, and the outputs frequency spectrum presents a higher purity. So the PLL circuits have the characteristic of high-speed and low-noise.
Key words: PLL; Charge Pump; noise figure